SH7730 Datasheet, PDF (796/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Figure 23.2 is a sample flowchart for initializing the SCIFA.
Initialization
Clear TE and RE bits in SCASCAR to 0 (1)
Set TFRST and RFRST bits in
SCAFCR to 1
Set CKE[1:0] bits in SCASCAR
(leaving TE and RE bits cleared to 0)
Set operating clock source in SCASMR (2)
Set value in SCABRR
(3)
Wait
No
1-bit interval elapsed?
(4)
Yes
Set RTRG1, RTRG0,
TTRG1, and TTRG0 in SCAFCR
Clear TFRST and RFRST bits to 0
(1) Set the clock selection in SCASCAR.
Be sure to clear bits RIE TIE, TE, and RE
to 0.
(2) Set the operating clock source in SCASMR.
(3) Write a value corresponding to the bit rate
into SCABRR.
(Not necessary if an external clock is used.)
(4) Wait at least one bit interval, then set the
TE bit or RE bit in SCASR to 1. Also set the
RIE and TIE bits.
Setting the TE and RE bits enables the
TXD and RXD pins to be used. When
transmitting, the line will go to the mark
state; when receiving, it will go to the idle
state.
Set TE and RE bits in
SCASCAR to 1,and set RIE,
and TIE bits
End
Figure 23.2 Sample SCIFA Initialization Flowchart
Rev. 1.00 Sep. 19, 2007 Page 748 of 1136
REJ09B0359-0100