SH7730 Datasheet, PDF (1046/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
30.3.4 Operand Access Cycle Break
1. Table 30.4 shows the relation between the operand sizes specified using the match condition
setting register (CBR0 or CBR1) and the address bits to be compared for the operand access
cycle break.
Table 30.4 Relation between Operand Sizes and Address Bits to be Compared
Selected Operand Size
Address Bits to be Compared
Quadword
Address bits A31 to A3
Longword
Address bits A31 to A2
Word
Address bits A31 to A1
Byte
Address bits A31 to A0
Operand size is not included in the Address bits A31 to A3 for quadword access
match conditions
Address bits A31 to A2 for longword access
Address bits A31 to A1 for word access
Address bits A31 to A0 for byte access
The above table means that if address H'00001003 is set in the match address setting register
(CAR0 or CAR1), for example, the match condition is satisfied for the following access cycles
(assuming that all the other conditions are satisfied):
 Longword access to address H'00001000
 Word access to address H'00001002
 Byte access to address H'00001003
2. When the data value is included in the channel 1 match conditions:
If the data value is included in the match conditions, be sure to select the quadword, longword,
word, or byte as the operand size using the operand size select bit (SZ) of the match condition
setting register (CBR1), and also set the match data setting register (CDR1) and the match data
mask setting register (CDMR1). With these settings, the match condition is satisfied when
both of the address and data conditions are satisfied. The data value and mask control for byte
access, word access, and longword access should be set in bits 7 to 0, 15 to 0, and 31 to 0 in
the bits CDR1 and CDMR1, respectively. For quadword access, 64-bit data is divided into the
upper and lower 32-bit data units, and each unit is independently compared with the specified
condition. When either the upper or lower 32-bit data unit satisfies the match condition, the
match condition for the 64-bit data is determined to be satisfied.
Rev. 1.00 Sep. 19, 2007 Page 998 of 1136
REJ09B0359-0100