SH7730 Datasheet, PDF (1071/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 32 List of Registers
Section 32 List of Registers
32.1 Register Addresses
• Information on the on-chip I/O registers are listed for each functional module in the order of
the corresponding section numbers
• Access to reserved addresses, which are not shown in this list, is prohibited. If accessed,
operation at the time of access and the subsequent operation are not guaranteed.
• The access size is shown in the number of bits.
• For details on the individual registers, see the register description in the corresponding
sections.
Table 32.1 Register Configuration (1)
Module
Exception
Handling
MMU
Caches
Note: *
Name
TRAPA exception register
Abbreviation R/W
TRA
R/W
P4 Address*
H'FF00 0020
Area 7
Address*
H'1F00 0020
Access
Size
32
Exception event register
EXPEVT
R/W H'FF00 0024 H'1F00 0024 32
Interrupt event register
INTEVT
R/W H'FF00 0028 H'1F00 0028 32
Non-support detection exception register
EXPMASK R/W H'FF2F 0004 H'1F2F 0004 32
Page table entry high register
PTEH
R/W H'FF00 0000 H'1F00 0000 32
Page table entry low register
PTEL
R/W H'FF00 0004 H'1F00 0004 32
Translation table base register
TTB
R/W H'FF00 0008 H'1F00 0008 32
TLB exception address register
TEA
R/W H'FF00 000C H'1F00 000C 32
MMU control register
MMUCR
R/W H'FF00 0010 H'1F00 0010 32
Physical address space control register
PASCR
R/W H'FF00 0070 H'1F00 0070 32
Instruction re-fetch inhibit control register
IRMCR
R/W H'FF00 0078 H'1F00 0078 32
Page table entry assistance register
PTEA
R/W H'FF00 0034 H'1F00 0034 32
Cache control register
CCR
R/W H'FF00 001C H'1F00 001C 32
Queue address control register 0
QACR0
R/W H'FF00 0038 H'1F00 0038 32
Queue address control register 1
QACR1
R/W H'FF00 003C H'1F00 003C 32
On-chip memory control register
RAMCR
R/W H'FF00 0074 H'1F00 0074 32
P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
Rev. 1.00 Sep. 19, 2007 Page 1023 of 1136
REJ09B0359-0100