SH7730 Datasheet, PDF (626/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
20.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I²C bus interface, controls
transmission or reception, and selects master or slave mode, transmission or reception, and
transfer clock frequency in master mode.
Bit: 7
6
5
4
3
2
1
0
ICE RCVD MST TRS
CKS[3:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface Enable
0: This module is halted.
1: This module is enabled for transfer operations.
6
RCVD
0
R/W Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
MST
0
R/W Master/Slave Select
4
TRS
0
R/W Transmit/Receive Select
In master mode with the I²C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1.
Operating modes are selected as below according to
MST and TRS combination.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Rev. 1.00 Sep. 19, 2007 Page 578 of 1136
REJ09B0359-0100