SH7730 Datasheet, PDF (152/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
5.5.2 Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—general
illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot
FPU disable exception, and unconditional trap exception—are detected in the process of
instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.2.
Pipeline flow:
Instruction n
Instruction n + 1
Instruction n + 2
TLB miss (data access) [Legend]
I1 I2 I3 ID E1 E2 E3 WB
I1, I2, I3: Instruction fetch
I1 I2 I3 ID E1 E2 E3 WB
ID :
Instruction decode
General illegal instruction exception E1, E2, E3: Instruction execution
TLB miss (instruction access)
I1 I2 I3 ID E1 E2 E3 WB
(E2, E3 Memory access)
WB
Write-back
Instruction n + 3
I1 I2 I3 ID E1 E2 E3 WB
Order of detection:
General illegal instruction exception (instruction n + 1) and
TLB miss (instruction n + 2) are detected simultaneously
TLB miss (instruction n)
Order of exception handling:
TLB miss (instruction n)
Re-execution of instruction n
Program order
1
General illegal instruction exception
(instruction n + 1)
2
Re-execution of instruction n + 1
TLB miss (instruction n + 2)
3
Re-execution of instruction n + 2
Execution of instruction n + 3
4
Figure 5.2 Example of General Exception Acceptance Order
Rev. 1.00 Sep. 19, 2007 Page 104 of 1136
REJ09B0359-0100