SH7730 Datasheet, PDF (337/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Table 11.8 Register States in Each Operating Mode
Name
Common control register
Bus control register for CS0
Bus control register for CS2
Bus control register for CS3
Bus control register for CS4
Bus control register for CS5A
Bus control register for CS5B
Bus control register for CS6A
Bus control register for CS6B
Wait control register for CS0
Wait control register for CS2
Wait control register for CS3
Wait control register for CS4
Wait control register for CS5A
Wait control register for CS5B
Wait control register for CS6A
Wait control register for CS6B
SDRAM control register
Refresh timer control/status
register
Refresh timer counter
Refresh time constant register
SDRAM mode register
SDRAM mode register
Power-On
Abbreviation Reset
CMNCR
Initialized
CS0BCR
Initialized
CS2BCR
Initialized
CS3BCR
Initialized
CS4BCR
Initialized
CS5ABCR Initialized
CS5BBCR Initialized
CS6ABCR Initialized
CS6BBCR Initialized
CS0WCR
Initialized
CS2WCR
Initialized
CS3WCR
Initialized
CS4WCR
Initialized
CS5AWCR Initialized
CS5BWCR Initialized
CS6AWCR Initialized
CS6BWCR Initialized
SDCR
Initialized
RTCSR
Initialized
Software
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
RTCNT
RTCOR
SDMR2
SDMR3
Initialized
Initialized


Retained
Retained


Module
Standby Sleep

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained

Retained




Rev. 1.00 Sep. 19, 2007 Page 289 of 1136
REJ09B0359-0100