SH7730 Datasheet, PDF (931/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 27 D/A Converter (DAC)
27.4 Operation
The D/A converter incorporates two D/A channels that can operate individually.
The D/A converter executes D/A conversion while analog output is enabled by the D/A control
register (DACR). When the D/A data registers (DADR0 and DADR1) are modified, the D/A
converter immediately initiates the new data conversion. Setting the DAE bit in DACR to 1 starts
D/A conversion, and setting the DAOE1 or DAOE0 bit in DACR to 1 enables the output of the
conversion results of the corresponding channel.
An example of D/A conversion on channel 0 is shown below. The operation timing is shown in
figure 27.2.
1. Write data for conversion to DADR0.
2. Set the DAE and DAOE0 bits in DACR to 1. D/A conversion starts, and the DA0 output is
enabled. The result of conversion is output after the conversion has ended. The output value
will be (DADR0 contents/1024) × AVcc.
The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is
cleared to 0.
3. When D/A data register 0 (DMDR0) is modified, the conversion starts again.
The results are output after the conversion has ended.
4. When the DAOE0 bit is cleared to 0, analog output is disabled (high-impedance state).
DADR0 DACR
write cycle write cycle
Pφ
Address bus
DADR0
write cycle
DACR
write cycle
DADR0
Conversion data (1)
Conversion data (2)
DAE/DAOE0
DA0
High impedance
state
[Legend]
t_DCONV: D/A conversion time
t_DCONV
Conversion result (1)
Conversion
result (2)
t_DCONV
Figure 27.2 D/A Converter Operation Example
Rev. 1.00 Sep. 19, 2007 Page 883 of 1136
REJ09B0359-0100