SH7730 Datasheet, PDF (631/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
Bit
2 to 0
Bit Name
BC[2:0]
Initial
Value
000
R/W Description
R/W Bit Counter
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I²C bus format, the data is
transferred with one addition acknowledge bit. Should
be made between transfer frames. If these bits are set
to a value other than B'000, the setting should be made
while the SCL pin is low. The value returns to B'000 at
the end of a data transfer, including the acknowledge
bit. These bits are cleared by a power-on reset and in
software standby mode and module standby mode.
These bits are also cleared by setting the IICRST bit of
ICCR2 to 1.
000: 9 bits
001: 2 bits
010: 3 bits
011: 4 bits
100: 5 bits
101: 6 bits
110: 7 bits
111: 8 bits
Rev. 1.00 Sep. 19, 2007 Page 583 of 1136
REJ09B0359-0100