SH7730 Datasheet, PDF (763/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Section 23 Serial Communication Interface with FIFO A
(SCIFA)
This LSI has two channels (channel 4 and channel 5) of serial communication interface (SCIFA)
that includes FIFO buffers. The SCIFA can perform asynchronous and synchronous serial
communications. It has 64-stage FIFO registers for both transmission and reception, which allow
efficient high-speed continuous communication.
23.1 Features
• Asynchronous or synchronous mode can be selected for serial communication mode.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Six types of interrupts (asynchronous mode):
Transmit-data-stop, transmit-FIFO-data-empty, receive-FIFO-data-full, receive-error (framing
error/parity error), break-receive, and receive-data-ready interrupts. A common interrupt vector
is assigned to each interrupt source.
• Two types of interrupts (synchronous mode)
• The direct memory access controller (DMAC) can be activated to transfer data in the event of
transmit-FIFO-data-empty, transmit-data-stop, or receive-FIFO-data-full. Note that the transfer
request to the DMAC is common to transmit-FIFO-data-empty and transmit-data-stop.
• On-chip modem control functions (CTS and RTS)
• Transmit data stop function is available
• While the SCIFA is not used, it can be stopped by stopping the clock for it to reduce power
consumption.
• The number of data bytes in the transmit and receive FIFO registers and the number of receive
errors of the receive data in the receive FIFO register can be known.
• Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
SCIS3C0C_000020030200
Rev. 1.00 Sep. 19, 2007 Page 715 of 1136
REJ09B0359-0100