SH7730 Datasheet, PDF (156/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
5.6.2 General Exceptions
(1) Data TLB Miss Exception
• Source: Address mismatch in UTLB address comparison
• Transition address: VBR + H'00000400
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400.
To speed up TLB miss processing, the offset is separate from that of other exceptions.
Data_TLB_miss_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access ? H'0000 0040 : H'0000 0060;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0400;
}
Rev. 1.00 Sep. 19, 2007 Page 108 of 1136
REJ09B0359-0100