SH7730 Datasheet, PDF (953/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 28 I/O Port
28.12 Port L
Port L is an input/output port with the pin configuration shown in figure 28.11. Each pin has an
input pull-up MOS, which is controlled by the port L control register (PLCR) in the PFC.
Port L
PTL7 (input)/AN1 (input)
PTL6 (input)/ AN0 (input)
PTL5 (input)/DA0 (output)
PTL4 (input)/DA1 (output)
PTL1 (input)/IIC0_SCL (input/output)
PTL0 (input)/IIC0_SDA (input/output)
Figure 28.11 Port L
28.12.1 Port L Data Register (PLDR)
PLDR is a register that stores data for pins PTL7 to PTL4, PTL1, and PTL0. Bits PL7DT to
PL4DT, PL1DT, and PL0DT correspond to pins PTL7 to PTL4, PTL1, and PTL0. For pins that
function as general-purpose output pins, a read operation directly reads out the value from this
register. For pins that function as general-purpose input pins, a read operation reads out the level
on the corresponding pin.
Bit: 7
6
5
4
3
PL7DT PL6DT PL5DT PL4DT —
Initial value: 0
0
0
0
0
R/W: R R R R R
2
1
0
— PL1DT PL0DT
0
0
0
RRR
Initial
Bit
Bit Name Value R/W Description
7
PL7DT
0
R
Table 28.13 shows the function of PLDR.
6
PL6DT
0
R
5
PL5DT
0
R
4
PL4DT
0
R
3, 2 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PL1DT
0
R
Table 28.13 shows the function of PLDR.
0
PL0DT
0
R
Rev. 1.00 Sep. 19, 2007 Page 905 of 1136
REJ09B0359-0100