SH7730 Datasheet, PDF (210/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Bit
25, 24
Initial
Bit Name Value R/W

All 0
R
23 to 18 URB
000000 R/W
17, 16 
All 0
R
15 to 10 URC
000000 R/W
9
SQMD 0
R/W
8
SV
0
R/W
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Boundary
These bits indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB ≠
0.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Counter
These bits serve as a random counter for indicating the
UTLB entry for which replacement is to be performed
with an LDTLB instruction. This bit is incremented each
time the UTLB is accessed. If URB > 0, URC is cleared
to 0 when the condition URC = URB is satisfied. Also
note that if a value is written to URC by software which
results in the condition of URC > URB, incrementing is
first performed in excess of URB until URC = H'3F.
URC is not incremented by an LDTLB instruction.
Store Queue Mode
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
in case of user access)
Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
Rev. 1.00 Sep. 19, 2007 Page 162 of 1136
REJ09B0359-0100