SH7730 Datasheet, PDF (1030/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
• CBR1
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFE AIE
MFI
AIV
Initial value : 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
DBE
SZ
ETBE
Initial value : 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R R
876543210
CD
ID
RW
CE
000000000
R R/W R/W R/W R/W R R/W R/W R/W
Bit
Bit Name
31
MFE
30
AIE
29 to 24 MFI
Initial
Value
0
0
100000
R/W
R/W
R/W
R/W
Description
Match Flag Enable
Specifies whether or not to include the match flag value
specified by the MFI bit of this register in the match
conditions. When the specified match flag value is 1,
the condition is determined to be satisfied.
0: The match flag is not included in the match
conditions; thus, not checked.
1: The match flag is included in the match conditions.
ASID Enable
Specifies whether or not to include the ASID specified
by the AIV bit of this register in the match conditions.
0: The ASID is not included in the match conditions;
thus, not checked.
1: The ASID is included in the match conditions.
Match Flag Specify
Specifies the match flag to be included in the match
conditions.
000000: The MF0 bit of the CCMFR register
000001: The MF1 bit of the CCMFR register
Others: Reserved (setting prohibited)
Note: The initial value is the reserved value, but when 1
is written into CBR1[0], MFI must be set to
000000 or 000001. And note that the channel 1 is
not hit when MFE bit of this register is 1 and MFI
bits are 000001 in the condition of CCRMF.MF1
= 0.
Rev. 1.00 Sep. 19, 2007 Page 982 of 1136
REJ09B0359-0100