SH7730 Datasheet, PDF (252/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
7.8 Usage Notes
7.8.1 Note on Using LDTLB Instruction
When using an LDTLB instruction instead of software to a value to the MMUCR. URC, execute 1
or 2 below.
1. Place the TLB miss exception handling routine*¹ only in the P1, P2 area ,or the on-chip
memory so that all the instruction accesses*³ in the TLB miss exception handling routine
should occur solely in the P1, P2 area, or the on-chip memory. Clear the RP bit in the RAMCR
register to 0 (initial value), when the TLB miss exception handling routine is placed in the on-
chip memory.
Do not make an attempt to execute the FDIV or FSQRT instruction in the TLB miss exception
handling routine.
2. If a TLB miss exception occurs, add 1 to MMUCR.URC before executing an LDTLB
instruction.
Notes: 1. An exception handling routine is an entire set of instructions that are executed from the
address (VBR + offset) upon occurrence of an exception to the RTE for returning to the
original program or to the RTE delay slot.
2. Instruction accesses include the PREFI and ICBI instructions.
Rev. 1.00 Sep. 19, 2007 Page 204 of 1136
REJ09B0359-0100