SH7730 Datasheet, PDF (799/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Start
1 _bit
Parity Stop Start
Data _{bit bit bit}
Parity Stop
Data
bit bit
1
Serial data
0 D₀ D₁
D₇ 0/1 1 0 D₀ D₁
D₇ 0/1 1
Idle
state
(mark state)
TDFE
TEND
Transmit-FIFO-
Data written to
Transmit-FIFO-
data-empty
SCAFTDR and TDFE _data-empty
interrupt request flag read as 1 then interrupt request
cleared to 0 by Transmit-
FIFO-data-empty
interrupt handler
One frame
Figure 23.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
 Transmit data stop function
When the value of the SCATDSR register and the number of transmit data bytes match,
transmit operation stops. Setting the TSIE bit (interrupt enable bit) allows the generation of
an interrupt and activation of DMAC.
Figure 23.5 shows an example of the operation for transmit data stop function.
Transmit data
TxD
TSF flag
Start
bit
0 D0 D1
Parity Stop
bit bit
D6 D7 0/1
Start
bit
0 D0 D1
D6 D7 0/1
Figure 23.5 Example of Transmit Data Stop Function
Rev. 1.00 Sep. 19, 2007 Page 751 of 1136
REJ09B0359-0100