SH7730 Datasheet, PDF (115/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Instruction
Operation
FLOAT
FPUL,FRn
(float) FPUL → FRn
FMAC
FR0,FRm,FRn FR0*FRm + FRn → FRn
FMUL
FRm,FRn
FRn*FRm → FRn
FNEG
FRn
FRn ∧ H'8000 0000 → FRn
FSQRT FRn
√FRn → FRn
FSUB
FRm,FRn
FRn – FRm → FRn
FTRC
FRm,FPUL
(long) FRm → FPUL
Instruction Code
1111nnnn00101101
1111nnnnmmmm1110
1111nnnnmmmm0010
1111nnnn01001101
1111nnnn01101101
1111nnnnmmmm0001
1111mmmm00111101
Privileged T Bit
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Table 3.11 Floating-Point Double-Precision Instructions
Instruction
Operation
Instruction Code
FABS
DRn
DRn & H'7FFF FFFF FFFF
FFFF → DRn
1111nnn001011101
FADD
DRm,DRn DRn + DRm → DRn
1111nnn0mmm00000
FCMP/EQ DRm,DRn When DRn = DRm, 1 → T
Otherwise, 0 → T
1111nnn0mmm00100
FCMP/GT DRm,DRn When DRn > DRm, 1 → T
Otherwise, 0 → T
1111nnn0mmm00101
FDIV
DRm,DRn DRn /DRm → DRn
1111nnn0mmm00011
FCNVDS DRm,FPUL double_to_ float(DRm) → FPUL 1111mmm010111101
FCNVSD FPUL,DRn float_to_ double (FPUL) → DRn 1111nnn010101101
FLOAT
FPUL,DRn (float)FPUL → DRn
1111nnn000101101
FMUL
DRm,DRn DRn *DRm → DRn
1111nnn0mmm00010
FNEG
DRn
DRn ^ H'8000 0000 0000 0000 1111nnn001001101
→ DRn
FSQRT DRn
√DRn → DRn
1111nnn001101101
FSUB
DRm,DRn DRn – DRm → DRn
1111nnn0mmm00001
FTRC
DRm,FPUL (long) DRm → FPUL
1111mmm000111101
Privileged T Bit
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Comparison
result
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Comparison
result
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Rev. 1.00 Sep. 19, 2007 Page 67 of 1136
REJ09B0359-0100