SH7730 Datasheet, PDF (554/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
Initial
Bit
Bit Name Value R/W Description
0
TGFA
0
R/(W)* Compare Flag A
Status flag indicating a match with TPUn_TGRA
[Clearing condition]
Writing 0 to the TCFA bit after reading the bit when
TCFA = 1
[Setting condition]
A match between the values in TPUn_TCNT and
TPUn_TGRA
Note: * Writing a 0 is the only way to clear this flag.
16.4.6 Timer Counter (TPUn_TCNT)
TPUn_TCNT indicates a 16-bit counter. The TPU has one TPUn_TCNT per channel.
TPUn_TCNT is initialized to H'0000 by a reset.
16.4.7 Timer General Register (TPUn_TGR)
TPUn_TGR indicates a 16-bit general register. Four general registers (TPUn_TGRA,
TPUn_TGRB, TPUn_TGRC, and TPUn_TGR) are provided for each channel. TPUn_TGRC and
TPUn_TGRD can be designated for operation as buffer registers*. TPUn_TGR is initialized to
H'FFFF by a reset.
Note: * The combination of TPUn_TGR and buffer register are TPUn_TGRATPUn_TGRC
and TPUn_TGRBTPUn_TGRD.
Rev. 1.00 Sep. 19, 2007 Page 506 of 1136
REJ09B0359-0100