SH7730 Datasheet, PDF (881/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
Initial
Bit
Bit Name Value R/W Description
1
RST
0
R/W Smart Card Reset
Controls the output of the SIM_RST pin of the smart
card interface.
0: SIM_RST pin of the smart card interface outputs low
level
1: SIM_RST pin of the smart card interface outputs high
level
0
SMIF
1
R Smart Card Interface Mode Select
This bit is always read as 1. The write value should
always be 1.
25.3.10 Serial Control 2 Register (SCSC2R)
SCSC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt
(RXI) requests.
Bit: 7
6
5
4
3
2
1
0
EIO — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R
Bit
7
6 to 0
Bit Name
EIO

Initial
Value
0
All 0
R/W Description
R/W Error Interrupt Only
When the EIO bit is 1, even if the RIE bit is set to 1, a
receive data full interrupt (RXI) request is not sent to the
CPU. When the DMAC is used with this setting, the
CPU processes only ERI requests.
0: Receive data full interrupt (RXI) requests are
determined by the RIE bit setting
1: Receive data full interrupt (RXI) requests are
disabled. When the RIE bit is 1, only ERI requests
are enabled.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 833 of 1136
REJ09B0359-0100