SH7730 Datasheet, PDF (710/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
data-full interrupt, and receive-error interrupts are requested independently on each channel.
• When the transmit FIFO is empty or the receive FIFO contains any received data, the DMA
controller (DMAC) can be activated to perform data transfer by generating a DMA transfer
request.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous mode, on-chip modem control functions (RTS and CTS) (channels 2 and 3).
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Rev. 1.00 Sep. 19, 2007 Page 662 of 1136
REJ09B0359-0100