SH7730 Datasheet, PDF (789/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Bit
Bit Name
13 to 11 
10 to 8 RSTRG
[2:0]
7, 6 RTRG[1:0]
Initial
Value R/W
All 0 R
000 R/W
00
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Trigger of the RTS Output Active
The RTS signal goes to high, when the number of
receive data bytes stored in SCAFRDR has become
equal to or more than the trigger number setting listed
below.
000: 63
001: 1
010: 8
011: 16
100: 32
101: 48
110: 54
111: 60
Receive FIFO Data Trigger Number
Set the number of receive data bytes at which the
receive data full (RDF) flag in SCASSR is set. The RDF
flag is set when the number of receive data bytes
stored in SCAFRDR has become equal to or more than
the trigger number setting listed below.
00: 1
01: 16
10: 32
11: 48
Rev. 1.00 Sep. 19, 2007 Page 741 of 1136
REJ09B0359-0100