SH7730 Datasheet, PDF (31/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Figure 10.3 Interrupt Operation Flowchart (when CPUOPM.INTMU = 0) ............................... 270
Figure 10.4 Interrupt Operation Flowchart (when CPUOPM.INTMU = 1) ............................... 271
Section 11 Bus State Controller (BSC)
Figure 11.1 Block Diagram of BSC............................................................................................ 279
Figure 11.2 Address Space ......................................................................................................... 283
Figure 11.3 Normal Space Basic Access Timing (Access Wait 0)............................................. 336
Figure 11.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword
Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) ....................... 338
Figure 11.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword
Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) ....................... 339
Figure 11.6 Example of 32-Bit Data-Width SRAM Connection ................................................ 340
Figure 11.7 Example of 16-Bit Data-Width SRAM Connection ................................................ 341
Figure 11.8 Example of 8-Bit Data-Width SRAM Connection .................................................. 341
Figure 11.9 Wait Timing for Normal Space Access (Software Wait Only) ............................... 342
Figure 11.10 Wait State Timing for Normal Space Access (Wait State Insertion using
WAIT Signal)........................................................................................................ 343
Figure 11.11 CSn Assert Period Expansion................................................................................ 344
Figure 11.12 Example of 32-Bit Data-Width SDRAM Connection ........................................... 346
Figure 11.13 Example of 16-Bit Data-Width SDRAM Connection ........................................... 347
Figure 11.14 Burst Read Basic Timing (Auto-Precharge).......................................................... 361
Figure 11.15 Burst Read Wait Specification Timing (Auto-Precharge) ..................................... 362
Figure 11.16 Basic Timing for Single Read (Auto-Precharge)................................................... 363
Figure 11.17 Basic Timing for Burst Write (Auto-Precharge) ................................................... 364
Figure 11.18 Basic Timing for Single Write (Auto-Precharge).................................................. 365
Figure 11.19 Burst Read Timing (No Auto-Precharge).............................................................. 367
Figure 11.20 Burst Read Timing (Bank Active, Same Row Address) ....................................... 368
Figure 11.21 Burst Read Timing (Bank Active, Different Row Addresses) .............................. 369
Figure 11.22 Single Write Timing (No Auto-Precharge) ........................................................... 370
Figure 11.23 Single Write Timing (Bank Active, Same Row Address) ..................................... 371
Figure 11.24 Single Write Timing (Bank Active, Different Row Addresses) ............................ 372
Figure 11.25 Auto-Refresh Timing ............................................................................................ 374
Figure 11.26 Self-Refresh Timing .............................................................................................. 376
Figure 11.27 Access Timing in Power-Down Mode .................................................................. 377
Figure 11.28 Write Timing for SDRAM Mode Register (Based on JEDEC)............................. 380
Figure 11.29 EMRS Command Issue Timing............................................................................. 382
Figure 11.30 Transition Timing in Deep Power-Down Mode .................................................... 383
Figure 11.31 Burst ROM (Clock Asynchronous) Access
(Bus Width = 32 Bits, 16-byte Transfer (Number of Bursts = 4), Access
Wait for First Time = 2, Access Wait for 2nd Time and after = 1)....................... 385
Figure 11.32 Basic Access Timing for Byte-Selection SRAM (BAS = 0) ................................. 386
Rev. 1.00 Sep. 19, 2007 Page xxxi of xlviii