SH7730 Datasheet, PDF (230/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
7.5.3 MMU Instruction (LDTLB)
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB
instruction is issued, this LSI copies the contents of PTEH and PTEL (also the contents of PTEA
in TLB extended mode) to the UTLB entry indicated by the URC bit in MMUCR. ITLB entries
are not updated by the LDTLB instruction, and therefore address translation information purged
from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes
address translation information, ensure that it is issued by a program in the P1 or P2 area.
After the LDTLB instruction has been executed, execute one of the following three methods
before an access (include an instruction fetch) the area where TLB is used to translate the address
is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the
area where TLB is used to translate the address.
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the LT bit in IRMCR is 0 (initial value) before executing the LDTLB instruction, the
specific instruction does not need to be executed. However, note that the CPU processing
performance will be lowered because the instruction fetch is performed again for the next
instruction after MMUCR has been updated.
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
Rev. 1.00 Sep. 19, 2007 Page 182 of 1136
REJ09B0359-0100