SH7730 Datasheet, PDF (681/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.10 Clock Select Register (SISCR)
SISCR is a 16-bit readable/writable register that sets the serial clock generation conditions for the
master clock. SISCR can be specified when the bits TRMD[1:0] in SIMDR are specified as B'10
or B'11.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSSEL MSIMM —
BRPS[4:0]
—————
BRDV[2:0]
Initial value: 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R/W R/W R/W R/W R/W R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15
MSSEL
1
R/W
14
MSIMM
1
R/W
13
—
0
R
12 to 8 BRPS[4:0] 00000 R/W
7 to 3 —
All 0 R
Description
Master Clock Source Selection
The master clock is the clock input to the baud rate
generator.
0: Uses the input signal of the SIOFMCK pin as the
master clock
1: Uses Pφ as the master clock
Master Clock Direct Selection
0: Uses the output clock of the baud rate generator as
the serial clock
1: Uses the master clock itself as the serial clock
Reserved
This bit is always read as 0. The write value should
always be 0.
Prescalar Setting
Set the master clock division ratio according to the
count value of the prescalar of the baud rate generator.
The range of settings is from B'00000 (× 1/1) to B'11111
(× 1/32).
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 633 of 1136
REJ09B0359-0100