SH7730 Datasheet, PDF (1147/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
33.4.8 Peripheral Module Signal Timing
Table 33.10 Peripheral Module Signal Timing
Conditions: V_CCQ = 3.0 to 3.6 V, V_CC = 1.1 to 1.3 V, AV_CC = 3.0 to 3.6 V, T_a = -20 to 75°C
Module
Port
DMAC
Item
Output data delay time
Input data setup time
Input data hold time
DREQn setup time
DREQn hold time
DACKn, TENDn delay time
Symbol Min.
t
PORTD

t
15
PORTS
t_PORTH
8
t_DREQS
6
t_DREQH
4
t
DACD

Max.
17




13
Unit Figure
ns 33.40
ns 33.41
33.42
CKO
Ports 7 to 0
(Read)
Ports 7 to 0
(Write)
t_PORTS t_PORTH
t_PORTD
Figure 33.40 I/O Port Timing
CKO
DREQn*
t_DREQS t_DREQH
Note: * Waveform when active low is specificed for DREQn.
Figure 33.41 DREQ Input Timing (DREQ Low Level is Detected)
Rev. 1.00 Sep. 19, 2007 Page 1099 of 1136
REJ09B0359-0100