SH7730 Datasheet, PDF (617/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
19.4 Operation
19.4.1 Counter Operation
The operation of CMT counter n (n= 0 to 4) is commenced by writing 1 to the corresponding
STRn bit in CMSTR after making other register settings as required. Complete all of the settings
before starting counter operation. Do not change the register settings other than by clearing flag
bits.
The counter operates in one of two ways.
• One-Shot Operation
One-shot operation is selected by clearing the CMM bit in CMCSR to 0. When the value in
CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and
the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared.
To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF and
OVF bits in CMCSR are set to 1.
Value in
CMCNT
CMCOR
H'00000000
CMF = 1
OVF = 1 (When an overflow is detected)
Time
Figure 19.2 Counter Operation (One-Shot Operation)
• Free-Running Operation
Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in
CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared.
Rev. 1.00 Sep. 19, 2007 Page 569 of 1136
REJ09B0359-0100