SH7730 Datasheet, PDF (302/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.3.5 Interrupt Request Register 00 (INTREQ00)
INTREQ00 is an 8-bit register that indicates interrupt requests from external input pins IRQ7 to
IRQ0. This register value is not affected by interrupt mask with the INTPRI00 or INTMSK00
settings.
When edge-detection mode is set for an IRQ pin (ICR1.IRQnS = B'00 or B'01), an interrupt
request is cleared by writing 0 to the corresponding IRQn bit after reading IRQn = 1.
Bit: 7
6
5
4
3
2
1
0
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7
IRQ0
0
R/W
6
IRQ1
0
R/W
5
IRQ2
0
R/W
4
IRQ3
0
R/W
3
IRQ4
0
R/W
2
IRQ5
0
R/W
1
IRQ6
0
R/W
0
IRQ7
0
R/W
[Legend]
n = 0 to 7
Description
IRQn Interrupt Request
Indicates whether there is an interrupt request input to
the IRQn pin.
[When edge-detection mode is selected (ICR1.IRQnS =
B'00 or B'01)]
• When reading
0: No interrupt request has been detected
1: Interrupt request has been detected
• When writing
0: Each bit is cleared by writing 0 after reading 1
1: Writing 1 is ignored
[When level-detection mode is selected (ICR1.IRQnS =
B'10 or B'11)]
• When reading
0: The corresponding interrupt pin has not been
asserted
1: The corresponding interrupt pin has been
asserted
but the interrupt request has not been accepted
by the CPU
• When writing
Writing 0 or 1 is ignored
Rev. 1.00 Sep. 19, 2007 Page 254 of 1136
REJ09B0359-0100