SH7730 Datasheet, PDF (810/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
(b) Serial Data Transmission
Figures 23.16 and 23.17 show sample flowcharts for serial transmission.
Start of transmission
Write remaining transmit data to SCAFTDR 1
Set TE bit in SCASCAR
When using transmit FIFO data interrupt, 2
set TIE bit to 1
1. Write the remaining transmit
data to SCAFTDR.
2. Transmission is started when
the TE bit in SCASCR is set to 1.
3. After the end of transmission,
clear the TE bit to 0.
TEND =1?
Yes
Clear TE bit in SCASCR to 0
End of transmission
No
3
Figure 23.16 Sample Serial Transmission Flowchart (1)
(First Transmission after Initialization)
Rev. 1.00 Sep. 19, 2007 Page 762 of 1136
REJ09B0359-0100