SH7730 Datasheet, PDF (659/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3 Register Descriptions
Table 21.2 shows the SIOF register configuration. Table 21.3 shows the register states in each
operating mode.
Table 21.2 Register Configuration
Name
Mode register
Clock select register
Transmit data assign register
Receive data assign register
Control data assign register
Control register
FIFO control register
Status register
Interrupt enable register
Transmit data register
Receive data register
Transmit control data register
Receive control data register
Abbreviation R/W
SIMDR
R/W
SISCR
R/W
SITDAR
R/W
SIRDAR
R/W
SICDAR
R/W
SICTR
R/W
SIFCTR
R/W
SISTR
R/W
SIIER
R/W
SITDR
W
SIRDR
R
SITCR
R/W
SIRCR
R/W
Address
H'A441 0000
H'A441 0002
H'A441 0004
H'A441 0006
H'A441 0008
H'A441 000C
H'A441 0010
H'A441 0014
H'A441 0016
H'A441 0020
H'A441 0024
H'A441 0028
H'A441 002C
Access Size
16
16
16
16
16
16
16
16
16
32
32
32
32
Rev. 1.00 Sep. 19, 2007 Page 611 of 1136
REJ09B0359-0100