SH7730 Datasheet, PDF(167/1188 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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SH7730 Datasheet, PDF (167/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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Section 5 Exception Handling

(10) Slot Illegal Instruction Exception

â¢ Sources:

ï£§ Decoding of an undefined instruction in a delay slot

Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S

Undefined instruction: H'FFFD

ï£§ Decoding of an instruction that modifies PC in a delay slot

Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,

BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR, ICBI, PREFI

ï£§ Decoding in user mode of a privileged instruction in a delay slot

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC

instructions that access GBR

ï£§ Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot

ï£§ The BRDSSLP bit in EXPMASK is 0, and the SLEEP instruction in the delay slot is

executed.

ï£§ The RTEDS bit in EXPMASK is 0, and an instruction other than the NOP instruction in the

delay slot is executed.

â¢ Transition address: VBR + H'000 0100

â¢ Transition operations:

The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and

R15 contents when this exception occurred are saved in SSR and SGR.

Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a

branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other

than H'FFFD is decoded.

Slot_illegal_instruction_exception()

{

SPC = PC - 2;

SSR = SR;

SGR = R15;

EXPEVT = H'0000 01A0;

SR.MD = 1;

SR.RB = 1;

SR.BL = 1;

PC = VBR + H'0000 0100;

}

Rev. 1.00 Sep. 19, 2007 Page 119 of 1136

REJ09B0359-0100

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