SH7730 Datasheet, PDF (599/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 18 Timer Unit (TMU)
18.2 Register Descriptions
Table 18.1 shows the TMU register configuration. Table 18.2 shows the register states in each
operating mode. In the following descriptions, TCOR for channel 0 is noted as TCOR_0.
Table 18.1 Register Configuration
Register
Timer start register
Timer constant register_0
Timer counter_0
Timer control register_0
Timer constant register_1
Timer counter_1
Timer control register_1
Timer constant register_2
Timer counter_2
Timer control register_2
Abbreviation
TSTR
TCOR_0
TCNT_0
TCR_0
TCOR_1
TCNT_1
TCR_1
TCOR_2
TCNT_2
TCR_2
R/W Address
R/W H'FFD80004
R/W H'FFD80008
R/W H'FFD8000C
R/W H'FFD80010
R/W H'FFD80014
R/W H'FFD80018
R/W H'FFD8001C
R/W H'FFD80020
R/W H'FFD80024
R/W H'FFD80028
Access Size
8
32
32
16
32
32
16
32
32
16
Table 18.2 Register States in Each Operating Mode
Register Abbreviation Power-On Reset Software Standby Module Standby Sleep
TSTR
Initialized
Retained
Retained
Retained
TCOR_0
Initialized
Retained
Retained
Retained
TCNT_0
Initialized
Retained
Retained
Retained
TCR_0
Initialized
Retained
Retained
Retained
TCOR_1
Initialized
Retained
Retained
Retained
TCNT_1
Initialized
Retained
Retained
Retained
TCR_1
Initialized
Retained
Retained
Retained
TCOR_2
Initialized
Retained
Retained
Retained
TCNT_2
Initialized
Retained
Retained
Retained
TCR_2
Initialized
Retained
Retained
Retained
Rev. 1.00 Sep. 19, 2007 Page 551 of 1136
REJ09B0359-0100