SH7730 Datasheet, PDF (502/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
13.4.1 Frequency Control Register (FRQCR)
FRQCR is a 32-bit readable/writable register used to specify the frequency multiplication ratio of
the PLL circuit, and the frequency division ratio of the CPU clock, SH clock, bus clock, and
peripheral clock. FRQCR can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HIGH[1:0] —
STC[4:0]
IFC[3:0]
————
Initial value: 0
0 —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹
R/W: R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SFC[3:0]
BFC[3:0]
————
PFC[3:0]
Initial value: —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹ —*¹
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W
Bit
31, 30
Bit Name
HIGH[1:0]
29
—
28 to 24 STC[4:0]
Initial
Value
R/W Description
00
R/W VCO selection for PLL circuit
Set according to the output frequency of the PLL
circuit.
00: PLL circuit operates at high speed (PLL circuit
multiplication output is 150 MHz or more)
01: Setting prohibited
10: Setting prohibited
Undefined*¹
Undefined*¹
R
R/W
11: PLL circuit operates at low speed (PLL circuit
multiplication output is 150 MHz or less)
Reserved
PLL Circuit Multiplication Ratio
Multiplication is by (setting + 1).
00001: ×2
00010: ×3
00011: ×4
00101: ×6
00111: ×8
01111: ×16
Other settings are prohibited
Rev. 1.00 Sep. 19, 2007 Page 454 of 1136
REJ09B0359-0100