SH7730 Datasheet, PDF (211/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Bit
7
6 to 3
2
1
0
Section 7 Memory Management Unit (MMU)
Initial
Bit Name Value
ME
0

All 0
TI
0

0
AT
0
R/W Description
R/W TLB Extended Mode Switching
0: TLB compatible mode
1: TLB extended mode
For modifying the ME bit value, always set the TI bit to
1 to invalidate the contents of ITLB and UTLB.
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
R
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
R/W Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is
0. In the case of software that does not use the MMU,
the AT bit should be cleared to 0.
Rev. 1.00 Sep. 19, 2007 Page 163 of 1136
REJ09B0359-0100