SH7730 Datasheet, PDF (461/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.7 DMA Channel Control Registers (CHCR_0 to CHCR_5)
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit: 31 30 29
— LCKN —
Initial value: 0
0
0
R/W: R R/W R
28 27 26 25 24 23 22 21 20 19 18 17 16
—
RPT[2:0]
— DO — TS[3:2] HE HIE AM AL
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R R/W R/W R/(W)* R/W R/W R/W
Bit: 15 14 13 12 11 10 9
DM[1:0]
SM[1:0]
RS[3:0]
8
7
6
5
4
3
DL DS TB TS[1:0]
2
1
0
IE TE DE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W
Initial
Bit
Bit Name Value R/W Descriptions
31
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30
LCKN
0
R/W Bus Release Enable in Cycle Steal Mode
Specifies whether to release the bus to a bus master
other than the DMAC between reading and writing in
cycle steal mode.
With the initial setting, the DMAC retains the bus
mastership. Setting this bit to 1 allows acceptance of
bus requests from a bus master other than the DMAC,
which increases the bus usage rate of the overall
system.
This bit can be set in cycle steal mode. Do not set it to 1
in burst mode.
0: Bus release between reading and writing is disabled
1: Bus release between reading and writing is enabled
Rev. 1.00 Sep. 19, 2007 Page 413 of 1136
REJ09B0359-0100