SH7730 Datasheet, PDF (45/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 18 Timer Unit (TMU)
Table 18.1 Register Configuration.......................................................................................... 551
Table 18.2 Register States in Each Operating Mode .............................................................. 551
Table 18.3 TMU Interrupt Sources ......................................................................................... 559
Section 19 Compare Match Timer (CMT)
Table 19.1 Register Configuration.......................................................................................... 563
Table 19.2 Register States in Each Operating Mode .............................................................. 564
Section 20 I²C Bus Interface (IIC)
Table 20.1 Pin Configuration.................................................................................................. 575
Table 20.2 Register Configuration.......................................................................................... 576
Table 20.3 Register States in Each Operating Mode .............................................................. 577
Table 20.4 Transfer Rate ........................................................................................................ 579
Table 20.5 Interrupt Requests ................................................................................................. 606
Table 20.6 Time for Monitoring SCL..................................................................................... 607
Section 21 Serial I/O with FIFO (SIOF)
Table 21.1 Pin Configuration.................................................................................................. 610
Table 21.2 Register Configuration.......................................................................................... 611
Table 21.3 Register States in Each Operating Mode .............................................................. 612
Table 21.4 Operation in Each Transfer Mode......................................................................... 615
Table 21.5 SIOF Serial Clock Frequency ............................................................................... 639
Table 21.6 Serial Transfer Modes........................................................................................... 641
Table 21.7 Frame Length........................................................................................................ 642
Table 21.8 Audio Mode Specification for Transmit Data....................................................... 644
Table 21.9 Audio Mode Specification for Receive Data ........................................................ 644
Table 21.10 Setting Number of Channels in Control Data ................................................... 645
Table 21.11 Conditions to Issue Transmit Request .............................................................. 647
Table 21.12 Conditions to Issue Receive Request ................................................................ 648
Table 21.13 Transmit and Receive Reset.............................................................................. 653
Table 21.14 SIOF Interrupt Sources ..................................................................................... 654
Section 22 Serial Communication Interface with FIFO (SCIF)
Table 22.1 Pin Configuration.................................................................................................. 664
Table 22.2 Register Configuration.......................................................................................... 665
Table 22.3 Register States in Each Operating Mode .............................................................. 667
Table 22.4 SCSMR Settings ................................................................................................... 686
Table 22.5 SCSMR Settings and SCIF Communication Formats........................................... 692
Table 22.6 Serial Communication Formats (Asynchronous Mode)........................................ 694
Rev. 1.00 Sep. 19, 2007 Page xlv of xlviii