SH7730 Datasheet, PDF (818/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
(3) Break Detection and Processing
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCAFRDR is halted in the break state, the SCIFA receiver continues to operate.
(4) Receive Data Sampling Timing and Receive Margin
An example with a sampling rate 1/16 is given. The SCIFA operates on a base clock with a
frequency of 8 times the transfer rate. In reception, the SCIFA synchronizes internally with the
fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge
of the eighth base clock pulse. The timing is shown in figure 23.22.
Base clock
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5
−7.5 clocks
+7.5 clocks
Receive data (RXD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 23.22 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00 Sep. 19, 2007 Page 770 of 1136
REJ09B0359-0100