SH7730 Datasheet, PDF (213/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Bit
Bit Name
31 to 8 
Initial
Value
All 0
7 to 0 UB
H'00
R/W Description
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or in
the cache write-through mode, these bits specify
whether the next bus access from the CPU waits for the
end of writing for each area.
0 : Buffered write (The CPU does not wait for the end of
writing bus access and starts the next bus access)
1 : Unbuffered write (The CPU waits for the end of
writing bus access and starts the next bus access)
UB[7]: Corresponding to the control register area
UB[6]: Corresponding to area 6
UB[5]: Corresponding to area 5
UB[4]: Corresponding to area 4
UB[3]: Corresponding to area 3
UB[2]: Corresponding to area 2
UB[1]: Corresponding to area 1
UB[0]: Corresponding to area 0
Rev. 1.00 Sep. 19, 2007 Page 165 of 1136
REJ09B0359-0100