SH7730 Datasheet, PDF (786/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.9 Bit Rate Register (SCABRR)
SCABRR is an eight-bit readable/writable register that, together with the baud rate generator clock
source selected by the CKS[1:0] bits in SCASMR, determines the serial transmit/receive bit rate.
Bit: 7
6
5
4
3
2
1
0
SCBRD[7:0]
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
SCBRD[7:0]
Initial
Value R/W
H'FF R/W
Description
Bit Rate Setting
The SCABRR setting is calculated as follows:
Asynchronous Mode:
1. When sampling rate is 1/16
N=
Pφ
× 10⁶ - 1
32 × 2^2n-1 × B
2. When sampling rate is 1/5
N=
Pφ
× 10⁶ - 1
10 × 2^2n-1 × B
3. When sampling rate is 1/11
N=
Pφ
× 10⁶ - 1
22 × 2^2n-1 × B
4. When sampling rate is 1/13
N=
Pφ
× 10⁶ - 1
26 × 2^2n-1 × B
5. When sampling rate is 1/27
N=
Pφ
× 10⁶ - 1
54 × 2^2n-1 × B
Rev. 1.00 Sep. 19, 2007 Page 738 of 1136
REJ09B0359-0100