SH7730 Datasheet, PDF (413/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
(6) Single Write
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
Figure 11.18 shows the single write basic timing.
CKO
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1 Trwl
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 11.18 Basic Timing for Single Write (Auto-Precharge)
Rev. 1.00 Sep. 19, 2007 Page 365 of 1136
REJ09B0359-0100