SH7730 Datasheet, PDF (698/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
(2) Reception in Master Mode
Figure 21.10 shows an example of settings and operation for master mode reception.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
SIOF Settings
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for baud rate
generator
SIOF Operation
3
Start SIOFSCK output
Output serial clock
4
Set the FSE and RXE bits
in SICTR to 1
Set starting of frame synchronization _{Output frame synchronization}
signal output and enable reception _signal
Store SIOFRXD receive data in SIRDR
5
synchronously with SIOFSYNC
6
RDREQ = 1?
No
Yes
7
Read SIRDR
Read receive data
Issue receive transfer
request according to the
receive FIFO threshold
value
Reception
Transfer
No
ended?
8
Yes
Clear the RXE bit in SICTR to 0
End
Disable reception
End reception
Figure 21.10 Example of Receive Operation in Master Mode
Rev. 1.00 Sep. 19, 2007 Page 650 of 1136
REJ09B0359-0100