SH7730 Datasheet, PDF (52/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 1 Overview
Item
Features
On-chip memory • Three independent read/write ports
(IL memory)
 Instruction fetch access from the CPU
 8-/16-/32-bit operand access from the CPU
 8-/16-/32-/64-bit or 16-/32-byte access from the DMAC
• Total of 16 Kbytes
Interrupt
• 21 external interrupt pins (NMI, IRQ7 to IRQ0, PINTA7 to PINTA0, PINTB3
controller (INTC)
to PINTB0)
 NMI: Fall/rise detection selectable
 IRQ: Fall/rise/high-level/low-level detection selectable
• 15-level coded external interrupts: IRL3 to IRL0 (shared with IRQ3 to IRQ0)
• On-chip peripheral interrupts: Priority can be specified for each module
Bus state
• Supports physical address space for areas of up to 32 Mbytes, up to 64
controller (BSC)
Mbytes, and up to 128 Mbytes each.
• The following functions can be set independently for each area
 Data bus width: 8, 16, or 32 bits (16 or 32 bits for area 0)
 Number of access wait cycles: For some areas, different wait cycles can
be specified for read and write accesses
 Idle wait cycle setting: For continuous access to the same area and to a
different area
 Supports SRAM, bust ROM, SDRAM, SRAM with byte-select function,
and PCMCIA by specifying memory to be connected to each area.
 Outputs a chip select signals, CS0, CS2 to CS4, CS5A/CS5B, or
CS6A/CS6B to the target area
• SDRAM
 Up to two 512-Mbit memory devices or up to one 1-Gbit memory device
can be connected
 Data bus width: 16 bits or 32 bits
 Supports auto-refresh, self-refresh, and partial refresh functions
 Supports deep power-down mode
 Auto-precharge mode or bank active mode can be selected
Rev. 1.00 Sep. 19, 2007 Page 4 of 1136
REJ09B0359-0100