SH7730 Datasheet, PDF (501/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
13.3 Clock Operating Modes
Table 13.2 shows the relationship between the mode control pin (MD1 and MD0) combinations
and the initial clock settings after a power-on reset.
Table 13.2 Clock Operating Modes
Clock ^{Pin Setting}
Mode MD1 MD0
0
00
1
01
2
10
3
11
Register
Initial Value
FRQCR
PLLCR
H'0755 5558 H'0000 4000
H'0700 0000 H'0000 0000
H'0755 5558 H'0000 4000
Clock
Source
PLL
(Multiplication
Initial Clock Ratio
Ratio)
Iφ Sφ Bφ Pφ
EXTAL ON (×8)
2221
EXTAL OFF
1/2 1/2 1/2 1/2
Crystal ON (×8)
oscillator
2221
Setting prohibited
13.4 Register Descriptions
Table 13.3 shows the CPG register configuration. Table 13.4 shows the register states in each
operating mode.
Table 13.3 Register Configuration
Register Name
Abbreviation R/W
Frequency control register
FRQCR
R/W
PLL control register
PLLCR
R/W
IrDA clock
IrDACLKCR
R/W
Oscillation settling time watch OSCWTCR
R/W
timer control register
Address
H'A415 0000
H'A415 0024
H'A415 0018
H'A415 0044
Access Size
32
32
32
32
Table 13.4 Register States in Each Operating Mode
Register Abbreviation Power-On Reset Software Standby
FRQCR
Initialized
Retained
PLLCR
Initialized
Retained
IrDACLKCR
Initialized
Retained
OSCWTCR
Initialized
Retained
Module Standby Sleep

Retained

Retained

Retained
—
Retained
Rev. 1.00 Sep. 19, 2007 Page 453 of 1136
REJ09B0359-0100