SH7730 Datasheet, PDF (143/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
5.2.2 Exception Event Register (EXPEVT)
The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code
set in EXPEVT is that for a reset or general exception event. The exception code is set
automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
EXPCODE
Initial value: 0
0
0
0
0
0
0
0
0
0 0/1 0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 12 
Initial
Value
All 0
11 to 0 EXPCODE H'000 or
H'020
R/W
R
R/W
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Exception Code
The exception code for a reset or general exception is
set. For details, see table 5.3.
Rev. 1.00 Sep. 19, 2007 Page 95 of 1136
REJ09B0359-0100