SH7730 Datasheet, PDF (254/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 8 Caches
Table 8.2 Store Queue Features
Item
Capacity
Addresses
Write
Write-back
Access right
Store Queues
32 bytes × 2
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction (PREF instruction)
When MMU is disabled: Determined by SQMD bit in MMUCR
When MMU is enabled: Determined by PR for each page
The operand cache of this LSI is 4-way set associative, each may comprising 256 cache lines.
Figure 8.1 shows the configuration of the operand cache.
The instruction cache is 4-way set-associative, each way comprising 256 cache lines. Figure 8.2
shows the configuration of the instruction cache.
This LSI has an IC way prediction scheme to reduce power consumption. In addition, memory-
mapped associative writing, which is detectable as an exception, can be enabled by using the non-
support detection exception register (EXPMASK). For details, see section 5, Exception Handling.
Rev. 1.00 Sep. 19, 2007 Page 206 of 1136
REJ09B0359-0100