SH7730 Datasheet, PDF (421/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
(8) Refreshing
This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by
clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can
be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long
period, self-refresh mode, in which the power consumption for data retention is low, can be
activated by setting both the RMODE bit and the RFSH bit to 1.
(a) Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0]
in RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be
set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings
for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and
RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up
from the value at that time. The RTCNT value is constantly compared with the RTCOR value,
and if the two values are the same, a refresh request is generated and an auto-refresh is
performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is
cleared to 0 and the count-up is restarted. Figure 11.25 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the
banks to precharged state from active state when some bank is being precharged. Then REF
command is issued in the Trr cycle after inserting idle cycles of which number is specified by
the TRP[1:0]bits in CSnWCR. A new command is not issued for the duration of the number of
cycles specified by the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must
be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is
inserted between the Tp cycle and Trr cycle when the setting value of the TRP[1:0] bits in
CSnWCR is longer than or equal to 2 cycles.
Rev. 1.00 Sep. 19, 2007 Page 373 of 1136
REJ09B0359-0100