SH7730 Datasheet, PDF (610/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
Figure 19.1 shows a block diagram of the CMT.
CMSTR
Pφ
Pre-scaler
CMT
CH0
CMCNT_0
CMCOR_0
CMCSR_0
Pre-scaler
CMCNT_1
Interrupt
control
CH1
CMCOR_1
Internal interrupt
DMA transfer
CMCSR_1
Pre-scaler
CMCNT_2
Interrupt
control
CH2
CMCOR_2
Internal interrupt
DMA transfer
CMCSR_2
Pre-scaler
CMCNT_3
Interrupt
control
CH3
CMCOR_3
Internal interrupt
DMA transfer
CMCSR_3
Pre-scaler
CMCNT_4
Interrupt
control
CH4
CMCOR_4
Internal interrupt
DMA transfer
CMCSR_4
Interrupt
control
Internal interrupt
DMA transfer
[Legend]
CMSTR:
CMCSR:
CMCNT:
CMCOR:
Compare match timer start register
Compare match timer control/status register
Compare match timer counter
Compare match timer constant register
Figure 19.1 Block Diagram of CMT
Rev. 1.00 Sep. 19, 2007 Page 562 of 1136
REJ09B0359-0100