SH7730 Datasheet, PDF (350/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
HW[1:0] 00
R/W Number of Delay Cycles from RD/WEn Negation to
Address/CSn Negation
Specify the number of delay cycles from RD or WEn
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS2WCR, CS3WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — BW[1:0] PMD BAS —
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — SW[1:0]
WR[3:0]
WM — — — — HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 24 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
23, 22 BW[1:0] 00
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted to the
second and subsequent access cycles in a burst
access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Note: Bit position is different from that of burst ROM
(asynchronous).
Rev. 1.00 Sep. 19, 2007 Page 302 of 1136
REJ09B0359-0100