SH7730 Datasheet, PDF (732/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
0
DR
0
R/W* Receive Data Ready
Indicates that the quantity of data in SCFRDR is less
than the specified receive trigger number, and that the
next data has not yet been received after the elapse
of 15 ETU from the last stop bit in asynchronous
mode. In clock synchronous mode, this bit is not set
to 1.
0: Reception is in progress, or no receive data
remains in SCFRDR after reception ended
normally.
[Clearing conditions]
• Power-on reset or manual reset
• After 1 is read from DR, all receive data are read
and then 0 is written to DR.
• All receive data are read by the DMAC
1: Next data has not been received
[Setting condition]
• SCFRDR contains less data than the specified
receive trigger number, and the next data has not
yet been received after the elapse of 15 ETU from
the last stop bit.
Note: 15 ETU is equivalent to 1.5 frames with the 8-
bit, 1-stop-bit format. (ETU: elementary time
unit)
Note: * Only 0 can be written to clear the flag.
Rev. 1.00 Sep. 19, 2007 Page 684 of 1136
REJ09B0359-0100