SH7730 Datasheet, PDF (769/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.1 Receive Shift Register (SCARSR)
SCARSR receives serial data. Data input at the RXD pin is loaded into the SCARSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCAFRDR, which is a receive FIFO data register. The CPU
cannot read from or write to the SCARSR directly.
23.3.2 Receive FIFO Data Register (SCAFRDR)
The 64-byte receive FIFO data register (SCAFRDR) stores serial receive data. The SCIFA
completes the reception of one byte of serial data by moving the received data from SCARSR into
SCAFRDR for storage. Continuous receive can be performed until 64 bytes are stored, which
makes SCAFRDR full.
The CPU can read but cannot write to SCAFRDR. When data is read without received data in
SCAFRDR, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
Bit: 7
6
5
4
3
2
1
0
SCFRD[7:0]
Initial value: — — — — — — — —
R/W: R R R R R R R R
Bit Bit Name
7 to 0 SCFRD[7:0]
Initial value
Undefined
R/W Description
R FIFO Data Registers for Serial Receive
Data
23.3.3 Transmit Shift Register (SCATSR)
SCATSR transmits serial data. The SCIFA loads transmit data from SCAFTDR into SCATSR,
then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data
byte, the SCI automatically loads the next transmit data from SCAFTDR into SCATSR and starts
transmitting again. The CPU cannot read or write SCATSR directly.
Rev. 1.00 Sep. 19, 2007 Page 721 of 1136
REJ09B0359-0100