SH7730 Datasheet, PDF (838/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
Initial
Bit
Bit Name Value R/W Description
9
—
1
R Reserved
This bit is always read as 1. The write value should
always be 1.
8, 7
—
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
6
URSME
0
R Receive Sum Error Flag
This bit is set to 1 when any of the UART error flags
(receive parity error flag, receive framing error flag, or
receive overrun error flag) is set to 1, and is cleared to 0
when none of the UART error flags is set to 1. The error
flag is cleared when the receive data register is read by
the system. If the next data is received before the
receive data register is read, the error flag is updated
according to the latest received data status (previous
received data error flags are overwritten).
0: No error has occurred.
1: An error has occurred.
5
UROVE
0
R Receive Overrun Error Flag
This bit is set to 1 when the next received data is stored
in the UART receive data register before the previous
received data is read from the register by the system,
and is cleared to 0 when the receive data register is
read by the system. (The previous received data is
always overwritten with the latest received data.)
0: No error has occurred.
1: An error has occurred.
4
URFRE
0
R Receive Framing Error Flag
This bit is cleared to 0 when the stop bits added behind
the UART received data matches the stop bit length
specified in the UART mode register, and is set to 1
when they do not match. The error flag is cleared when
the receive data register is read by the system. If the
next data is received before the receive data register is
read, the error flag is updated according to the latest
received data status (previous received data error flags
are overwritten).
0: No error has occurred.
1: An error has occurred.
Rev. 1.00 Sep. 19, 2007 Page 790 of 1136
REJ09B0359-0100