SH7730 Datasheet, PDF (470/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
9, 8
7 to 3
2
Bit
Name
PR[1:0]
Initial
Value
00
—
All 0
AE
0
R/W Description
R/W Priority Mode
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Address Error Flag
Indicates that an address error interrupt occurred during
DMA transfer.
This bit is set under following conditions:
• The value set in SAR or DAR does not match to the
transfer size boundary.
• The transfer source or transfer destination is invalid
space.
• The transfer source or transfer destination is in
module stop mode
If this bit is set, DMA transfer is disabled even if the DE
bit in CHCR and the DME bit in DMAOR are set to 1.
0: No DMAC address error interrupt
[Clearing condition]
• Writing AE = 0 after AE = 1 read
1: DMAC address error interrupt occurs
Rev. 1.00 Sep. 19, 2007 Page 422 of 1136
REJ09B0359-0100